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====== ULA (Named HCS 10017) ======

There is no official datasheet (impossible to find one on the internet).

This chip needs a 12 MHz clock on its CLK_IN pin. CLK_OUT pin sents an 1 MHz clock to the CPU.


| {{oric:hardware:ula10017_v2.png|}}     | {{oric:hardware:synp_ula.png|}}          |

  * D0-D7 Data bus (only read no write from ULA)
  * Red, Blue, Green : RGB signals
  * VSS : 5V
  * A8 to A15 Address bus
  * MA0 to MA7 : address bus RAM
  * W write signal for RAM
  * RAS/CAS
  * Mux : external multiplexer command
  * Sync : Sync video signal
  * MAP : Disable/enable internal decoding address bus ?
  * CLK_IN : 12 MHz
  * CLK_OUT : 1 MHz


----


* Mux is high when CLKOUT is high : This means that the address from the cpu are ok. This means that mux will help to switch A0 to A7 and MA0 to MA7. If MUX=1 : A0 to A7 are enabled with RAS. If Mux=0 MA0 and MA7 are enabled by cas.

* MA0 and MA7 outputs are a mirror of A8 to A15 inputs. Ula generate RAS, CAS and W : It needs to inverts MA0, MA7 to run normally

* when Mux is low, it's the graphics part of the ULA which access to ram to draw the screen

* in the case of an access from #0300 to #03FF, or #C000 TO #FFFF, the chip does not generate CAS signal. (fig4)

* MAP signal must be forced to 1, in normal configuration. If MAP switched to 0, it allow to access to shadow ram (#C000 TO #FFFF)

====== Fig 4 ======
{{oric:hardware:chrono_ula_1.png|}}

====== Fig 3 ======
{{oric:hardware:chrono_ula_2.png|}}

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