oric:hardware:cpu_65c02
- A0-A15 Address Bus
- BE Bus Enable
- D0-D7 Data Bus
- IRQB Interrupt Request
- MLB Memory Lock
- NC No Connection
- NMIB Non-Maskable Interrupt
- PHI1O Phase 1 Out Clock
- PHI2 Phase 2 In Clock
- PHI2O Phase 2 Out Clock
- RDY Ready
- RESB Reset
- RWB Read/Write
- SOB Set Overflow
- SYNC Synchronize
- VDD Positive Power Supply
- VPB Vector Pull
- VSS Internal Logic Ground
How to connect a 65C02 in an Oric
VP must not connected (pin 1)
BE must be connected to RDY (Pin 36 to pin 2)
oric/hardware/cpu_65c02.txt · Last modified: 2011/07/20 17:30 by polluks
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution-Share Alike 4.0 International
