oric:hardware:cpu_65c816
A0-A15 Address Bus
ABORTB Abort Input
BE Bus Enable
PHI2 Phase 2 In Clock
D0-D7 Data Bus/Bank Address Bus
E Emulation OR Native Mode Select
IRQB Interrupt Request
MLB Memory Lock (useful in multiprocessors system)
MX Memory and Index Register Mode Select
NC No Connect
NMIB Non-Maskable Interrupt
RDY Ready
RESB Reset
RWB Read/Write
VDA Valid Data Address
VPB Vector Pull
VPA Valid Program Address
VDD Positive Power Supply
VSS Internal Logic Ground
oric/hardware/cpu_65c816.txt · Last modified: 2009/06/28 00:28 by jede